IBIS Macromodel Task Group

Meeting date: 28 May 2013

Members (asterisk for those attending):
Agilent:                    * Fangyi Rao
                            * Radek Biernacki
Altera:                     * David Banas
                              Julia Liu
                              Hazlina Ramly
Andrew Joy Consulting:        Andy Joy
ANSYS:                        Samuel Mertens
                            * Dan Dvorscak
                            * Curtis Clark
                              Steve Pytel
                              Luis Armenta
Arrow Electronics:            Ian Dodd
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
                              Feras Al-Hawari
                              Brad Brim
                              Kumar Keshavan
                              Ken Willis
Cavium Networks:              Johann Nittmann
Celsionix:                    Kellee Crisafulli
Cisco Systems:                Ashwin Vasudevan
                              Syed Huq
Ericsson:                     Anders Ekholm
IBM:                          Greg Edlund
Intel:                      * Michael Mirmak
Maxim Integrated Products:    Mahbubul Bari
                            * Hassan Rafat
                              Ron Olisar
Mentor Graphics:            * John Angulo
                              Zhen Mu
                            * Arpad Muranyi
                              Vladimir Dmitriev-Zdorov
Micron Technology:            Randy Wolff
                              Justin Butterfield
NetLogic Microsystems:        Ryan Couts
Nokia-Siemens Networks:       Eckhard Lenski
QLogic Corp.                  James Zhou
SiSoft:                     * Walter Katz
                              Todd Westerhoff
                              Doug Burns
                            * Mike LaBonte
Snowbush IP:                  Marcus Van Ierssel
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group:   Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla
                              Ray Anderson

The meeting was led by Arpad Muranyi

------------------------------------------------------------------------
Opens:

- Arpad: Our agenda is full, we should try to avoid getting stuck

- David: There were emails on BIRD 158.3, we should leave time for that

--------------------------
Call for patent disclosure:

- None

-------------
Review of ARs:

- Fangyi submit updated BIRD 156 to Open Forum
  - Done

- Mike post update BIRD 156 to ATM web
  - Submitted to open forum instead

-------------
New Discussion:

Interconnect Task Group report:
- Michael M:
  - EMD document review was tabled, we did a summit review instead.
  - Some scrubbing needs to be done on terminology.
  - We will be revisiting BIRD 161.1 next week.
- Arpad: Should BIRD 161.1 be discussed in this meeting?
- Michael M: We can keep it in the interconnect group until further notice
  - It probably will miss IBIS 6 either way.

BIRD 158:
- Arpad showed BIRD 158
- Bob: I think there is confusion on what the input is.
- Arpad: There was a contradiction in defining the unit step.
  - Walter updated this, but Radek had an email comment on it.
- Radek: The step response is a measurement taken with a unit step input.
  - The source voltages really are controlled by other unit step sources
  - It is not made clear that the sources shown only scale the input.
- David: The rise time is called instantaneous, then it is admitted that that is impossible.
  - It should say the step rise time is one sample interval.
- Mike L: Should it be "simulator time step"?
- Fangyi: The simulator may have a coarser time step than the sample step.
- David: The vector going into the simulation is what matters.

- Walter: This discussion is independent of BIRD 158.
- David: The BIRD discusses this, so it is relevant.
- Walter: It is a generic problem, but BIRD 158 is the only place it is discussed.
  - There are other methods to generate an impulse response.
  - If not in BIRD 158, IBIS should discuss impulse response generation somewhere.
- Radek: It is a separate issue and should have a separate BIRD.

- Todd: Fangyi said the step goes in, but we read the response as an output.
  - For example 10Gbs at 8samples/bit would send 80G samples/sec to AMI_Init.
  - This is an impulse response, not delta-Dirac.
  - I can derive the response using any bandwidth I want.
- Walter: That is 12.5ps time step, but the SPICE simulation may have 1ps time step.
- Arpad: David was talking about the case where the simulation time step is coarser.
- David: No one would ever characterize a channel at lower bandwidth than what is passed to AMI_Init.
- Todd: This is not specific to BIRD 158, it is a generic problem.
- Fangyi: The simulator does not need to put in a small time step based on calculated bandwidth.
- David: How do we set a limit on bandwidth without over-constraining?
- Todd: The data sent to the model requires a certain interval, and we assume it is valid.
- Arpad: The [Model] keyword has no limit on voltage.
  - Should we have defined a unit step response?
- Radek: The sources shown in the diagram as not necessarily the excitation.
  - There should be an input controlling these sources.
- Arpad: The analog model should be characterized with EQ off.
  - This BIRD is consistent with that.
- Todd: We use "step response" and "impulse response" imprecisely.
  - AMI responses are not mathematical responses.
  - The request here is to have that shown explicitly.
- David: I think we only need to talk about magnitude units.
- Bob: Is this talking about voltages or scaling?
- Radek: It would be the actual voltage.
  - The picture just needs to be explained.

- Arpad: The gain scaling could be put in the s-parameter too.
- Todd: When we worked with Agilent a year ago we thought scaling outside the s-parameter would be easier
- Arpad: I agree with Radek that the wording needs to be more precise.
- Walter: We also have to support process corners.
  - Where the voltage is the only difference it is convenient to have scaling outside the s-parameter.
- Todd: It would be best to avoid the term "step response".
- Walter: The BIRD uses the term "Step Response Stimulus" to differentiate.
- Fangyi: Yes that is important.
  - Also an IBIS [Model] is still driven by an event.
- Todd: A lossy network will not produce a response with area = 1.
- Walter: Wikipedia distinguishes between an impulse response and unit impulse response.
  - An impulse response simply maintains its area.
  - A unit response is the special case with area 1.

- Radek: There was also an issue about common mode.
- Walter: Where the TX and RX operate at different voltages the RX may be operated outside its linear region.
  - The Touchstone output should be able to mimic what legacy IBIS does.
- Radek: The analysis ignores common mode.
- Arpad: If operated at the wrong voltage the response may be wrong.
- Radek: The ground is not clear and it may change.
- Todd: Customers want plug and play.
  - If the receiver is HSPICE the waveform may be nonsense if biased wrong.

Arpad showed the Redriver BIRD 156:
- Arpad: Do we need the word "units" near "volts"?
  - Also should resampling consider the RX_Receiver_Noise value?
- Todd: We have no "X" state here, only 0 and 1.
  - The PLL can't adapt that fast.
- Arpad: Without a sensitivity range the state changes immediately above and below zero.
- Walter: The sampling happens 1/2 UI after clock ticks.
- Todd described a voltage/time scenario.
- Walter: Only the voltage at clock tick times matter, not transitions.
  - Otherwise there would be a jitter problem.
- Todd: This is an example why having the model do processing makes sense.
  - That allows for sublink error analysis.

-------------
Next meeting: 04 June 2013 12:00pm PT

-------------
IBIS Interconnect SPICE Wish List:

1) Simulator directives